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參數(shù)資料
| 型號： | R5F64201JFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 14/103頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | R5F64201JFB |
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REJ03B0236-0110 Rev.1.10 Mar 02, 2010
Page 16 of 97
R32C/120 Group
2. Central Processing Unit (CPU)
2.1.8.5
Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the
register bank 1 is selected.
2.1.8.6
Overflow Flag (O flag)
This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0.
2.1.8.7
Interrupt Enable Flag (I flag)
This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable
them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.
2.1.8.8
Stack Pointer Select Flag (U flag)
To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set
this flag to 1.
It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a
software interrupt number from 0 to 127 is executed.
2.1.8.9
Floating-point Underflow Flag (FU flag)
This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.10
Floating-point Overflow Flag (FO flag)
This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.11
Processor Interrupt Priority Level (IPL)
The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority
level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the
selected IPL.
When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.
2.1.8.12
Fixed-point Radix Point Designation Bit (DP bit)
This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result
to take. It is used in the MULX instruction.
2.1.8.13
Floating-point Rounding Mode (RND)
The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.
2.1.8.14
Reserved
Only set this bit to 0. The read value is undefined.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| R5F64201KFB | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| R5F6420FLFB | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| R5F64201LFB | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| R5F6420EKFB | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| R5F64200JFB | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F64201KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64201LFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64206JFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64206JFB_12 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64206KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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