參數(shù)資料
型號: R5F64166PFD
元件分類: 微控制器/微處理器
英文描述: 64-BIT, FLASH, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 87/98頁
文件大小: 782K
代理商: R5F64166PFD
REJ03B0253-0110
Rev.1.10
Page 88 of 95
Jun 23, 2010
R32C/116 Group
5. Electrical Characteristics
VCC =3.3 V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta =Topr, unless otherwise noted)
Note:
1.
The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
tsu(S-ALE) = tsu(A-ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]
tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) - 20 [ns]
tw(R) = Tw(R) × tc(Base) -10 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]
Table 5.62
External Bus Timing (Multiplexed bus)
Symbol
Characteristic
Measurement
condition
Value
Unit
Min.
Max.
tsu(S-ALE)
Chip-select setup time for ALE
Refer to
Figure 5.6
(1)
ns
th(R-S)
Chip-select hold time after read
1.5 × tc(Base) - 15
ns
tsu(A-ALE)
Address setup time for ALE
(1)
ns
th(ALE-A)
Address hold time after ALE
0.5 × tc(Base) - 5
ns
th(R-A)
Address hold time after read
1.5 × tc(Base) - 15
ns
td(ALE-R)
ALE-read delay time
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(ALE)
ALE pulse width
(1)
ns
tdis(R-A)
Address disable time after read
8ns
tw(R)
Read pulse width
(1)
ns
th(W-S)
Chip-select hold time after write
1.5 × tc(Base) - 15
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 15
ns
td(ALE-W)
ALE-write delay time
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0.5 × tc(Base)
ns
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