
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 13 of 99
R32C/111 Group
1. Overview
1.4
Pin Assignments
Figure 1.5 to Figure 1.8 show the pin assignments (top view) and Table 1.8 to Table 1.14 show the pin
characteristics.
Figure 1.5
Pin Assignment for the 100-pin Package (top view)
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
100
99
98
97
96
95
94
93
92
91
90
89
87
86
85
84
83
82
81
80
79
78
77
76
75
74
88
73
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT (Note 2)
P6_7 / TXD1 / SDA1 / SRXD1
AVCC
VREF
AN_0 / P10_0
AVSS
AN_1 / P10_1
AN_2 / P10_2
AN_3 / P10_3
KI0 / AN_4 / P10_4
KI1 / AN_5 / P10_5
KI2 / AN_6 / P10_6
KI3 / AN_7 / P10_7
AN0_0 / D0 / P0_0
AN0_1 / D1 / P0_1
AN0_2 / D2 / P0_2
AN0_3 / D3 / P0_3
AN0_4 / D4 / P0_4
AN0_5 / D5 / P0_5
AN0_6 / D6 / P0_6
AN0_7 / D7 / P0_7
P6_6 / RXD1 / SCL1 / STXD1
P6_5 / CLK1
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_3 / TXD0 / SDA0 / SRXD0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_1 / TB1IN / CLK0
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P5_7 / RDY / CS3 / CTS7 / RTS7
P5_6 / ALE / CS2 / RXD7
P5_5 / HOLD / CLK7
P5_4 / HLDA / CS1 / TXD7
R5_3 / CLKOUT / BCLK
P5_2 / RD
P5_1 / WR1 / BC1
P5_0 / WR0 / WR
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_5 / CS2 / A21 / CLK6
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6
CLK4 / ANEX0 / P9_5
S
4
/
RTS
4
/CT
S4
/
T
B
4IN
/
DA
1
/
P9
_4
VD
C0
P9
_1
VD
C1
NS
D
CN
VS
S
X
C
IN
/
P8
_7
XCO
U
T
/
P8
_6
R
ESE
T
XOU
T
VS
S
XI
N
VC
C1
NM
I/
P8
_5
IN
T
2
/
P8
_4
IN
T
1
/
P8
_3
IN
T
0
/
P8
_2
UD
0B
/
U
D
1
B
/IIO
1_
5
/
R
T
S
5
/
C
T
S5
/
S
5
/
U
/
T
A
4IN
/
P8
_1
UD
0A
/
U
D
1
A
/
R
X
D5
/S
C
L
5
/
STX
D
5
/
U
/
T
A
4O
U
T
/
P8
_0
UD
0
B
/
UD
1B
/IIO
1
_4
/CL
K5
/
T
A
3IN
/
P7
_7
U
D
0
A
/
UD
1
A
/
I
IO1
_3
/
RT
S
8
/
CTS
8
/
TXD
5
/
SD
A
5
/
SR
XD5
/
T
A
3O
U
T
/
P7
_6
IIO1
_
2
/
RX
D8
/
W
/
T
A
2IN
/
P7
_5
II
O1
_1
/CL
K8
/
W
/
T
A
2O
U
T
/
P7
_4
II
O
1_0
/
T
X
D
8
/
SS2
/
R
T
S2
/
CTS
2
/V
/
T
A
1IN
/
P7
_3
P7_2 / TA1OUT / V / CLK2
P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN
T
B
3IN
/
DA
0
/
P9
_3
IIO0_1 / IIO1_1 / D9 / P1_1
IIO0_2 / IIO1_2 / D10 / P1_2
P
1
_
3
/
D1
1
/
IIO0
_
3
/
II
O1_
3
P
1
_
4
/
D1
2
/
IIO0
_
4
/
II
O1_
4
P
1
_
5
/D1
3
/INT
3
/IIO0
_
5
/
II
O
1
_5
P
1
_
6
/D1
4
/INT
4
/IIO0
_
6
/
II
O
1
_6
P
1
_
7
/D1
5
/INT
5
/IIO0
_
7
/
II
O
1
_7
P
2
_
0
/
A0
/
[A0
/D0]
/B
C
0
/
[B
C0/D
0
]/
AN
2
_
0
VS
S
P
3
_
0
/
A8
/
[A8
/D8]
/TA
0O
UT
/
U
D
0
A
/
UD
1A
VCC
2
P
3
_
1
/
A9
/
[A9
/D9]
/TA
3O
UT
/
U
D
0
B
/
UD
1B
P
3
_
2
/
A1
0
/
[A1
0
/D
10]
/
T
A
1
O
UT
/
V
P
3
_
3
/
A1
1
/
[A1
1
/D
11]
/
T
A
1
IN
/
V
P
3
_
4
/
A1
2
/
[A1
2
/D
12]
/
T
A
2
O
UT
/
W
P
3
_
5
/
A1
3
/
[A1
3
/D
13]
/
T
A
2
IN
/
W
P
3
_
6
/
A1
4
/
[A1
4
/D
14]
/
T
A
4
O
UT
/
U
P
3
_
7
/
A1
5
/
[A1
5
/D
15]
/
T
A
4
IN
/
U
P
4
_
0
/
A1
6
/
CTS
3
/
RT
S3
/
SS
3
P
4
_
1
/
A1
7
/
CLK
3
P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN
P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT
P
2
_
1
/
A1
/
[A1
/D1]
/A
N
2_
1
P
2
_
2
/
A2
/
[A2
/D2]
/A
N
2_
2
P
2
_
3
/
A3
/
[A3
/D3]
/A
N
2_
3
P
2
_
4
/
A4
/
[A4
/D4]
/A
N
2_
4
P
2
_
5
/
A5
/
[A5
/D5]
/A
N
2_
5
P
2
_
6
/
A6
/
[A6
/D6]
/A
N
2_
6
P
2
_
7
/
A7
/
[A7
/D7]
/A
N
2_
7
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IIO0_0 / IIO1_0 / D8 / P1_0
PLQP0100KB-A
(100P6Q-A)
(Top view)
R32C/111 GROUP
(Note 1)
(Note 3)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. Pins P7_0 and P7_1 are open drain outputs.
3. The position of pin number 1 varies by product. Refer to the index mark attached “Package Dimensions”.
VCC1
VCC2
(Note 2)