參數(shù)資料
型號: R5F56104VNFP
元件分類: 微控制器/微處理器
英文描述: 64-BIT, FLASH, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 69/85頁
文件大?。?/td> 1355K
代理商: R5F56104VNFP
RX610 Group
5. Electrical Characteristics
R01DS0097EJ0100
Rev.1.00
Page 71 of 83
Apr 22, 2011
Table 5.8
Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V,
Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications)
Item
Symbol
Min. *1*2
Max.
Unit
Test
Conditions
SCL input cycle time
tSCL
8(10) x (1/PCLK) + 240
ns
SCL input high pulse width
tSCLH
3(5) x (1/PCLK) + 120
ns
SCL input low pulse width
tSCLL
5 x (1/PCLK) + 120
ns
SCL, SDA input rising time
tSr
120
ns
SCL, SDA input falling time
tSf
120
ns
SCL, SDA input spike pulse removal
time
tSP
0
4 x (1/PCLK)
ns
SDA input bus free time
tBUF
5 x (1/PCLK) + 120
ns
Start condition input hold time
tSTAH
3(5) x (1/PCLK) +
120
ns
Re-start condition input setup time
tSTAS
5 x (1/PCLK) + 120
ns
Stop condition input setup time
tSTOS
3(5) x (1/PCLK) + 120
ns
Data input setup time
tSDAS
50
ns
Data input hold time
tSDAH
0
ns
RIIC
(Fast-mode+)
ICFER.FMPE = 1
SCL, SDA capacitive load
Cb
550
pF
Figure 5.25
TCK clock cycle time
tTCKcyc
100
ns
TCK clock high level pulse width
tTCKH
45
ns
TCK clock low level pulse width
tTCKL
45
ns
TCK clock rising time
tTCKr
5
ns
TCK clock falling time
tTCKf
5
ns
Figure 5.26
TRST# pulse width
tTRSTW
20
Tcyc
Figure 5.27
TMS setup time
tTMSS
20
ns
TMS hold time
tTMSH
20
ns
TDI setup time
tTDIS
20
ns
TDI hold time
tTDIH
20
ns
Boundary scan
(176-pin LFBGA)
TDO data delay time
tTDOD
40
ns
Figure 5.28
Notes:1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
2. Cb indicates the total capacity of the bus line.
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