參數(shù)資料
型號： R5F3650RNFB
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, LQFP-100
文件頁數(shù)： 3/81頁
文件大?。?/td> 879K
代理商： R5F3650RNFB
101
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a
strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the
forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero.
Bit 3 – WGM02: Waveform Generation Mode
Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
14.8.3
Timer/Counter Register – TCNT0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
14.8.4
Output Compare Register A – OCR0A
Table 14-9.
Clock Select Bit Description
CS02
CS01
CS00
Description
0
No clock source (Timer/Counter stopped)
001
clkI/O/(No prescaling)
010
clkI/O/8 (From prescaler)
011
clkI/O/64 (From prescaler)
100
clkI/O/256 (From prescaler)
101
clkI/O/1024 (From prescaler)
1
0
External clock source on T0 pin. Clock on falling edge.
1
External clock source on T0 pin. Clock on rising edge.
Bit
76543210
TCNT0[7:0]
TCNT0
Read/Write
R/W
Initial Value
00000000
Bit
76543210
OCR0A[7:0]
OCR0A
Read/Write
R/W
Initial Value
00000000
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