參數(shù)資料
型號(hào)： R5F363BENFE
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 115/115頁
文件大?。?/td> 2363K
代理商： R5F363BENFE
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 99 of 113
M16C/63 Group
5. Electrical Characteristics
Figure 5.31
Timing Diagram
Memory Expansion Mode and Microprocessor Mode
(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
BCLK
CSi
ADi
ALE
RD
BHE
ADi
/DBi
Read timing
BCLK
CSi
ADi
ALE
BHE
ADi
/DBi
Data output
WR,WRL,
WRH
Write timing
Address
Data input
Address
V
= V
= 3 V
CC1
CC2
td(BCLK-CS)
50ns(max.)
tcyc
(0.5
× t
-10)ns(min.)
cyc
th(RD-CS)
th(BCLK-CS)
0ns(min.)
(0.5
× t
-40ns(min.)
cyc
td(AD-ALE)
(0.5
× t
-15ns(min.)
cyc
th(ALE-AD)
tdz(RD-AD)
8ns(max.)
{(n-0.5)
× t
-60}ns(max.)
cyc
tac3(RD-DB)
tsu(DB-RD)
50ns(min.)
th(RD-DB)
0ns(min.)
td(AD-RD)
th(BCLK-AD)
0ns(min.)
25ns(max.)
td(BCLK-ALE)
th(BCLK-ALE)
-4ns(min.)
td(BCLK-AD)
50ns(max.)
th(RD-AD)
(0.5
× t
-10)ns(min.)
cyc
40ns(max.)
td(BCLK-RD)
0ns(min.)
th(BCLK-RD)
tcyc
td(BCLK-CS)
50ns(max.)
(0.5
× t
-10)ns(min.)
cyc
th(WR-CS)
th(BCLK-CS)
0ns(min.)
td(BCLK-DB)
50ns(max.)
th(BCLK-DB)
0ns(min.)
(0.5
× t
-40ns(min.)
cyc
td(AD-ALE)
{(n-0.5)
× t
-50}ns(min.)
cyc
td(DB-WR)
(0.5
× t
-10)ns(min.)
cyc
th(WR-DB)
td(BCLK-AD)
50ns(max.)
th(BCLK-AD)
0ns(min.)
25ns(max.)
td(BCLK-ALE)
th(BCLK-ALE)
-4ns(min.)
0ns(min.)
td(AD-WR)
th(WR-AD)
(0.5
× t
-10)ns(min.)
cyc
40ns(max.)
td(BCLK-WR)
0ns(min.)
th(BCLK-WR)
n: 2 (when 2 waits)
3 (when 3 waits)
Measuring conditions
V
= V
= 3 V
CC1
CC2
Input timing voltage: V = 0.6 V, V
= 2.4 V
IL
IH
Output timing voltage: V
= 1.5 V, V
= 1.5 V
OL
OH
1
t
=
cyc
f(BCLK)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F363BENFE#U0 制造商:Renesas Electronics Corporation 功能描述:M16C63 256+24/20KB -20 85C 80LQFP - Trays
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R5F36406CNFA 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:cameras, televisions, household appliances, office equipment
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