
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 11 of 113
M16C/63 Group
1. Overview
Figure 1.7
Pin Assignment for the 100-Pin Package
26
27
28
29
30
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P1_0/CTS6/RTS6/D8
P1_1/CLK6/D9
P1_2/RXD6/SCL6/D10
VREF
AVSS
AVCC
P10_0/AN0/KI4
P10_1/AN1/KI5
P10_2/AN2/KI6
P10_3/AN3/KI7
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_7/ADTRG/SIN4
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
M16C/63 Group
PLQP0100KB-A
(100P6Q-A)
(top view)
P1_
3
/TXD6
/SDA6/D11
P1_4
/D
12
P3_
1
/A9
P
3
_2
/A
10
P3_3
/A1
1
P3_4
/A1
2
P
3
_5
/A
13
P3_6
/A1
4
P3_7
/A1
5
P
4
_0
/A
16
P
4
_1
/A
17
VC
C2
VSS
P4_2/A18
P4_3/A19
P5_6/ALE
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
P5_7/RDY/CLKOUT
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P6_0/TRHO/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P5_0/WRL/WR
P5_1/WRH/BHE
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/SDAMM/TA0OUT (1)
VCC1
XI
N
XO
UT
VSS
RESET
C
N
VSS
P8_
7
/XC
IN
P8
_6/X
C
OU
T
BYTE
P7_4/
TA2O
U
T
/W
P9_
3
/DA0/T
B3IN/PWM
0
P9
_4/D
A
1/
TB4IN
/PW
M1
P9_
1
/T
B1IN/PMC1
/SIN3
P9
_2/TB2
IN/PM
C
0
/SOU
T
3
P8_2/
IN
T0
P8_3/
IN
T1
P
8
_
5
/N
MI
/S
D/
C
E
C
(1
)
P9
_0
/TB0IN
/CLK3
P8_
4
/IN
T
2/ZP
P7_
5
/T
A2IN/W
P7_
3
/CTS2
/RTS2/T
A1IN/V
P
7
_
6
/TA3OUT/TXD
5
/SDA5
P7
_7
/TA3IN
/CLK5
P8
_
0
/TA4O
U
T/U/RXD5/S
C
L
5
P8
_1
/TA4IN
/U
/CT
S
5/RTS5
P4_5/CLK7/CS1
P4_4/CTS7/RTS7/CS0
P3_0/
A8
[A8/D
7
]
P2_0/
AN
2_0
/A0,
[A0
/D0
],
A0
P2_1/
AN
2_1
/A1,
[A1
/D1
],
[A1
/D
0
]
P2_2/
AN
2_2
/A2,
[A2
/D2
],
[A2
/D
1
]
P2_3/
AN
2_3
/A3,
[A3
/D3
],
[A3
/D
2
]
P2_4/
IN
T6/AN
2_4/
A4,
[A4
/D
4
],
[A4/D
3
]
P2_5/
IN
T7/AN
2_5/
A5,
[A5
/D
5
],
[A5/D
4
]
P2_6/
AN
2_6
/A6,
[A6/
D6
],
[A6
/D
5
]
P2_7/
AN
2_7
/A7,
[A7
/D7
],
[A7
/D
6
]
(See Note 3)
P1_
5
/INT3
/IDV/D13
P1_
6
/INT4
/IDW/D1
4
P1_7
/INT5
/IDU
/D
1
5
P4_6/PWM0/RXD7/SCL7/CS2
P4_7/PWM1/TXD7/SDA7/CS3
VCC2 ports
VCC1 ports
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate
functional signals.