參數(shù)資料
型號: R5F363AKDFB
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 96/115頁
文件大?。?/td> 2363K
代理商: R5F363AKDFB
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 81 of 113
M16C/63 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Switching Characteristics
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.2.4.5
In Wait State Setting 2
φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When
Inserting 1 to 3 Recovery Cycles and Accessing External Area
Notes:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
3.
This standard value shows the timing when the output is off, and does not
show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down)
resistance value.
Hold time of data bus is expressed in
t =
CR × ln(1V
OL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output
low level is
t =
30 pF × 1 kΩ × In(1 0.2V
CC2/VCC2)
= 6.7 ns.
4.
Calculated according to the BCLK frequency as follows:
Table 5.39
Memory Expansion and Microprocessor Modes (in Wait State Setting 2
φ + 3φ, 2φ + 4φ,
3
φ + 4φ, and 4φ + 5φ, and When Inserting 1 to 3 Recovery Cycles and Accessing
External Area)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
See
25
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
th(RD-AD)
Address output hold time (in relation to RD)
ns
th(WR-AD)
Address output hold time (in relation to WR)
ns
td(BCLK-CS)
Chip select output delay time
25
ns
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
td(BCLK-ALE)
ALE signal output delay time
15
ns
th(BCLK-ALE)
ALE signal output hold time
-4
ns
td(BCLK-RD)
RD signal output delay time
25
ns
th(BCLK-RD)
RD signal output hold time
0ns
td(BCLK-WR)
WR signal output delay time
25
ns
th(BCLK-WR)
WR signal output hold time
0ns
td(BCLK-DB)
Data output delay time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
0ns
td(DB-WR)
Data output delay time (in relation to WR)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
ns
td(BCLK-HLDA)
HLDA output delay time
40
ns
n
10
9
×
f
BCLK
()
------------------40 ns
[]
n is 3 for 2
φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
m
10
9
×
f
BCLK
()
-------------------10 ns
[]
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
DBi
R
C
m
10
9
×
f
BCLK
()
-------------------10 ns
[]
+
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
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