參數(shù)資料
型號： R5F363A6DFB
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 119/119頁
文件大小： 907K
代理商： R5F363A6DFB
R01DS0033EJ0200 Rev.2.00
Page 99 of 115
Feb 07, 2011
M16C/63 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Switching Characteristics
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.4.3
In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Notes:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
n is 2 for 2 waits setting, 3 for 3 waits setting.
3.
Calculated according to the BCLK frequency as follows:
4.
Calculated according to the BCLK frequency as follows:
5.
When using multiplexed bus, set f(BCLK) 12.5 MHz or less.
Table 5.59
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) (5)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
See
50
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
th(RD-AD)
Address output hold time (in relation to RD)
ns
th(WR-AD)
Address output hold time (in relation to WR)
ns
td(BCLK-CS)
Chip select output delay time
50
ns
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
th(RD-CS)
Chip select output hold time (in relation to RD)
ns
th(WR-CS)
Chip select output hold time (in relation to WR)
ns
td(BCLK-RD)
RD signal output delay time
40
ns
th(BCLK-RD)
RD signal output hold time
0ns
td(BCLK-WR)
WR signal output delay time
40
ns
th(BCLK-WR)
WR signal output hold time
0ns
td(BCLK-DB)
Data output delay time (in relation to BCLK)
50
ns
th(BCLK-DB)
Data output hold time (in relation to BCLK)
0ns
td(DB-WR)
Data output delay time (in relation to WR)
ns
th(WR-DB)
Data output hold time (in relation to WR)
ns
td(BCLK-ALE)
ALE signal output delay time (in relation to BCLK)
25
ns
th(BCLK-ALE)
ALE signal output hold time (in relation to BCLK)
4ns
td(AD-ALE)
ALE signal output delay time (in relation to Address)
ns
th(AD-ALE)
ALE signal output hold time (in relation to Address)
ns
td(AD-RD)
RD signal output delay from the end of address
0ns
td(AD-WR)
WR signal output delay from the end of address
0ns
tdz(RD-AD)
Address output floating start time
8ns
0.5
10
9
×
f
BCLK
()
----------------------10 ns
[]
–
n
0.5
–
() 10
9
×
f
BCLK
()
------------------------------------50 ns
[]
–
0.5
10
9
×
f
BCLK
()
----------------------40 ns
[]
–
0.5
10
9
×
f
BCLK
()
----------------------15 ns
[]
–
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PDF描述
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