參數(shù)資料
型號: R5F2L38CCNFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 53/74頁
文件大小: 959K
代理商: R5F2L38CCNFP
58
2588F–AVR–06/2013
ATtiny261/461/861
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between and 1 system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is one system clock period.
Figure 10-4. Synchronization when Reading a Software Assigned Pin Value
XXX
in r17, PINx
0x00
0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t pd, min
out PORTx, r16
nop
in r17, PINx
0xFF
0x00
0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
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相關代理商/技術參數(shù)
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