參數(shù)資料
型號(hào)： R5F2L38CCNFA
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 14 MM, 0.65 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 38/74頁(yè)
文件大?。?/td> 959K
代理商： R5F2L38CCNFA
44
2588F–AVR–06/2013
ATtiny261/461/861
8.1.4
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT. Refer to
“Watchdog Timer” on page 44 for details on operation of the Watchdog Timer.
Figure 8-6.
Watchdog Reset During Operation
8.2
Internal Voltage Reference
ATtiny261/461/861 features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator or the ADC. The bandgap
voltage varies with supply voltage and temperature, as can be seen in Figure 20-36 on page
8.2.1
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in “System and Reset Characteristics” on page 190. To save power, the
reference is not always turned on. The reference is on during the following situations:
1.
When the BOD is enabled (by programming the BODLEVEL [2:0] Fuse bits).
2.
When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3.
When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
8.3
Watchdog Timer
The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table
8-3 on page 49. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny261/461/861 resets and executes from the Reset
Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 49.
CK
CC
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