參數(shù)資料
型號(hào)： R5F2L36CCNFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 71/74頁
文件大?。?/td> 959K
代理商： R5F2L36CCNFP
74
2588F–AVR–06/2013
ATtiny261/461/861
Figure 11-3.
T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
clk_I/O/2.5.
An external clock source can not be prescaled.
11.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
11-4 shows a block diagram of the counter and its surroundings.
Table 11-2.
Counter Unit Block Diagram
Signal description (internal signals):
count
Increment or decrement TCNT0 by 1.
clk
Tn
Timer/Counter clock, referred to as clk
T0 in the following.
top
Signalize that TCNT0 has reached maximum value.
The counter is incremented at each timer clock (clk
T0) until it passes its TOP value and then
restarts from BOTTOM. The counting sequence is determined by the setting of the CTC0 bit
located in the Timer/Counter Control Register (TCCR0A). For more details about counting
T0 can be generated from an external or
Tn_sync
(To Clock
Select Logic)
Edge Detector
Synchronization
DQ
LE
DQ
Tn
clk
I/O
DATA BUS
TCNTn
Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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