
R8C/38T-A Group
18. Timer RE2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 347 of 730
Aug 05, 2011
[Conditions for setting to 0]
When 0 is written to this bit after reading it. If the result of reading this bit is 1, writing 0 to this bit will set it
to 0.
When an interrupt from the DTC is automatically cleared.
[Condition for setting to 1]
When the interrupt source enabled by the TREIER register occurs.
If the result of reading this bit is 0, writing 0 to this bit will not change its value. If this bit changes from 0 to 1
after the read, the bit will remain 1 even if 0 is written. Writing 1 has no effect.
Change this bits when the RUN bit in the TRECR register is 0 (count stops).
While the TADJSF bit is 1 (being corrected), do not change the following bits or register:
The AADJE bit in the TRECR register
The AADJM bit in the TRECSR register
The TREADJ register
[Conditions for setting to 0]
Correction ends.
(1) For addition correction, when the correction value set by bits ADJ0 to ADJ5 in the TREADJ register is
transferred to the internal counter.
(2) For subtraction correction, when the correction value set by bits ADJ0 to ADJ5 and the internal counter
value are compared and match.
When 00b (not corrected) is written to bits PLUS to MINUS in the TREADJ register.
[Conditions for setting to 1]
Correction by software
(1) When 01b (subtraction correction) is written to bits PLUS to MINUS (the TADJSF bit is set to 1 in
synchronization with the count source).
(2) When 10b (addition correction) is written to bits PLUS to MINUS (the TADJSF bit is set to 1 in
synchronization with the count source).
Automatic correction
When the BSY bit in the TRESEC register is set to 0 (data not being updated) during the seconds which meet
the conditions for subtraction correction.