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參數(shù)資料
| 型號(hào)： | R5F2138AFJFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 20 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 30/30頁 |
| 文件大?。?/td> | 483K |
| 代理商： | R5F2138AFJFP |
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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either
of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0A pin (DDR_OC0A) must be
set as output before the OC0A value is visible on the pin. The port override function is independent of the Wave-
form Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled.
Note that some COM0A1:0 bit settings are reserved for certain modes of operation. See ”Register description” on
15.6.1
Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes. For all modes,
setting the COM0A1:0 = 0 tells the Waveform Generator that no action on the OC0A Register is to be performed on
the next compare match. For compare output actions in the non-PWM modes refer to Table 15-3 on page 94. For
fast PWM mode, refer to Table 15-4 on page 94, and for phase correct PWM refer to Table 15-5 on page 94.
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-
PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits.
15.7
Modes of operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM0A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a
compare match (See ”Compare Match Output Unit” on page 87.)
For detailed timing information refer to Figure 15-8 on page 92, Figure 15-9 on page 92, Figure 15-10 on page 92
15.7.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-
bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
15.7.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The
OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the
compare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 15-5 on page 89. The counter value (TCNT0) increases
until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.
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