
R8C/36T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 279 of 728
Aug 05, 2011
17.2
Registers
17.2.1
Timer RC Counter (TRCCNT)
The input clock for the timer RC counter is selected by bits CKS0 to CKS2 in the TRCCR1 register. By setting
the CCLR bit in the TRCCR1 register to 1 in advance, the TRCCNT register is set to 0000h at a compare match
with the TRCCRA register.
Do not access the TRCCNT register in 8-bit units. This register must be accessed in 16-bit units.
Table 17.4
Timer RC Register Configuration
Register Name
Symbol
After Reset
Address
Access Size
Timer RC_0 Counter
TRCCNT_0
0000h
00138h
16
Timer RC_0 General Register A
TRCGRA_0
FFFFh
0013Ah
16
Timer RC_0 General Register B
TRCGRB_0
FFFFh
0013Ch
16
Timer RC_0 General Register C
TRCGRC_0
FFFFh
0013Eh
16
Timer RC_0 General Register D
TRCGRD_0
FFFFh
00140h
16
Timer RC_0 Mode Register
TRCMR_0
01001000b
00142h
8
Timer RC_0 Control Register 1
TRCCR1_0
00h
00143h
8
Timer RC_0 Interrupt Enable Register
TRCIER_0
01110000b
00144h
8
Timer RC_0 Status Register
TRCSR_0
01110000b
00145h
8
Timer RC_0 I/O Control Register 0
TRCIOR0_0
10001000b
00146h
8
Timer RC_0 I/O Control Register 1
TRCIOR1_0
10001000b
00147h
8
Timer RC_0 Control Register 2
TRCCR2_0
00011000b
00148h
8
Timer RC_0 Digital Filter Function Select Register
TRCDF_0
00h
00149h
8
Timer RC_0 Output Enable Register
TRCOER_0
01111111b
0014Ah
8
Timer RC_0 A/D Conversion Trigger Control Register
TRCADCR_0
11110000b
0014Bh
8
Timer RC_0 Output Waveform Manipulation Register
TRCOPR_0
00h
0014Ch
8
Timer RC_0 ELC Cooperation Control Register
TRCELCCR_0
00h
0014Dh
8
Address 00138h (TRCCNT_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
————
———
—
After Reset
0
000
0000
Bit
b15
b14
b13
b12
b11
b10
b9
b8
Symbol
————
———
—
After Reset
0
000
0000
Bit
Function
Setting Range
R/W
b15 to b0 16-bit readable/writable up counter.
When this counter overflows, the OVF bit in the TRCSR register is set to 1.
If the OVIE bit in the TRCIER register is set to 1 (interrupt request (FOVI) by
OVF bit is enabled) at this time, an interrupt request is generated.
0000h to FFFFh
R/W