參數(shù)資料
型號(hào): R5F2136CCNFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 37/62頁
文件大小: 581K
代理商: R5F2136CCNFP
R8C/2A Group, R8C/2B Group
5. Electrical Characteristics
Rev.2.10
Nov 26, 2007
Page 40 of 60
REJ03B0182-0210
NOTES:
1.
The measurement condition is Topr = -20 to 85
°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2.
This condition (external power VCC rise gradient) does not apply if VCC
≥ 1.0 V.
3.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4.
tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if
20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if
40°C ≤ Topr < 20°C.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
Table 5.10
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
Vpor1
Power-on reset valid voltage(4)
0.1
V
Vpor2
Power-on reset or voltage monitor 0 reset valid
voltage
0
Vdet0
V
trth
External power VCC rise gradient(2)
20
mV/msec
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual for details.
Vdet0(3)
Vpor1
Internal
reset signal
(“L” valid)
tw(por1)
Sampling time(1, 2)
Vdet0(3)
1
fOCO-S
× 32
1
fOCO-S
× 32
Vpor2
2.2V
External
Power VCC
trth
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