參數(shù)資料
型號(hào): R5F212DCSNFP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù): 11/62頁(yè)
文件大?。?/td> 508K
代理商: R5F212DCSNFP
R8C/2C Group, R8C/2D Group
2. Central Processing Unit (CPU)
Rev.2.10
Dec 05, 2007
Page 17 of 57
REJ03B0183-0210
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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