
R8C/2C Group, R8C/2D Group
15. Serial Interface
Rev.2.00
Dec 05, 2007
REJ09B0339-0200
Figure 15.6
Registers U0C1 to U2C1 and U0RB to U2RB
UARTi Transmit/Receive Control Register 1 (i = 0 to 2)
Symbol
Address
After Reset
U0C1
00A5h
00000010b
U1C1
00ADh
00000010b
U2C1
0165h
00000010b
Bit Symbol
Bit Name
Function
RW
NOTES:
1.
2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.
UARTi transmit interrupt cause
select bit
0 : Transmission buffer empty (TI=1)
1 : Transmission completed (TXEPT=1)
RW
UiRRM
UARTi continuous receive mode
enable bit(2)
0 : Disables continuous receive mode
1 : Enables continuous receive mode
RW
The RI bit is set to 0 w hen the higher byte of the UiRB register is read out.
—
(b7-b6)
RO
RW
RI
Receive complete flag(1)
0 : No data in UiRB register
1 : Data in UiRB register
RE
RW
TI
RO
0 : Data in UiTB register
1 : No data in UiTB register
TE
—
Receive enable bit
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Transmit enable bit
0 : Disables transmission
1 : Enables transmission
Transmit buffer empty flag
0 : Disables reception
1 : Enables reception
UiIRS
UARTi Receive Buffer Register (i = 0 to 2)(1)
Symbol
Address
After Reset
U0RB
00A7h-00A6h
Undefined
U1RB
00AFh-00AEh
Undefined
U2RB
0167h-0166h
Undefined
RW
NOTES:
1.
2.
—
(b7-b0)
—
Function
Receive data (D7 to D0)
RO
Receive data (D8)
RO
—
(b8)
—
b0
b7
(b15)
b7
(b8)
b0
Bit Symbol
Bit Name
OER
Overrun error flag(2)
0 : No overrun error
1 : Overrun error
RO
0 : No parity error
1 : Parity error
RO
FER
Framing error flag(2)
0 : No framing error
1 : Framing error
RO
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
—
(b11-b9)
Read out the UiRB register in 16-bit units.
Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b
(serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no
error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte
of the UiRB register is read out.
Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.
RO
SUM
Error sum flag(2)
0 : No error
1 : Error
PER
Parity error flag(2)