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參數(shù)資料
| 型號(hào)： | R5F212BASNFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 14/138頁 |
| 文件大?。?/td> | 492K |
| 代理商： | R5F212BASNFP |
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199
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Note:
1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
18.8
Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
18.8.1
Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 18-6
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2X = 1) of operation. Samples
denoted zero are samples done when the RxD line is idle (i.e., no communication activity).
Figure 18-6. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in
the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-
ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
TABLE 2.
Assembly Code Example(1)
USART_Flush:
sbis
UCSRA, RXC0
ret
lds
r16, UDR
rjmp
USART_Flush
C Code Example
(1)
void
USART_Flush( void )
{
unsigned char
dummy;
while
( UCSRA & (1<<RXC0) ) dummy = UDR;
}
12
34
56
7
8
9
10
11
12
13
14
15
16
12
START
IDLE
0
BIT 0
3
123
4
5
678
12
0
RxDn
Sample
(U2Xn = 0)
Sample
(U2Xn = 1)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F212BASNFP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 96KB Flash 2.5V/3.3V/5V 64-Pin LQFP 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 96KB FLASH 2.5V/3.3V/5V 64LQFP - Trays 制造商:Renesas Electronics Corporation 功能描述:MCU R8C/2B 制造商:Renesas Electronics 功能描述:MCU 16-Bit R8C CISC 96KB Flash 2.5V/3.3V/5V 64-Pin LQFP 制造商:Renesas 功能描述:MCU 16-Bit R8C CISC 96KB Flash 2.5V/3.3V/5V 64-Pin LQFP |
| R5F212BASNFP#V0 | 功能描述:IC R8C/2B MCU FLASH 64LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/2B 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| R5F212BASNFP#V2 | 制造商:Renesas Electronics Corporation 功能描述:R8C/2B 96+2/7 64LQFP 10X10 -20 制造商:Renesas Electronics Corporation 功能描述:R8C/2B 96+2/7 64LQFP 10X10 -20 TO +85 - Trays 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT 96KB FLASH 64LQFP |
| R5F212BASNLG | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F212BASNLG#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 2/5V 96+2KB 64-TFLGA - Trays 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 96KB FLASH 64LGA |
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