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參數(shù)資料
| 型號： | R5F21264KXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 35/52頁 |
| 文件大小： | 620K |
| 代理商： | R5F21264KXXXFP |
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58
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
13.2
Register description
13.2.1
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 13-1.
The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
13.2.2
EIMSK – External Interrupt Mask Register
Bit 7 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is
enabled. Any change on any enabled PCINT30:24 pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCINT3 Interrupt Vector. PCINT30:24 pins are enabled individually
by the PCMSK3 Register.
Note:
1. This bit is a reserved bit in Atmel
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and should always be writ-
ten to zero.
Bit 6 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is
enabled. Any change on any enabled PCINT23:16 pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCINT2 Interrupt Vector. PCINT23:16 pins are enabled individually
by the PCMSK2 Register.
Note:
1. This bit is a reserved bit in Atmel
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and should always be writ-
ten to zero.
Bit
765
432
10
(0x69)
–
ISC01
ISC00
EICRA
Read/Write
RR
RRR
R
R/W
Initial Value
000
00
Table 13-1.
Interrupt 0 sense control.
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
Bit
7
6
543
210
0x1D (0x3D)
PCIE3 (1)
PCIE2 (1)
PCIE1
PCIE0
–
–INT0
EIMSK
Read/Write
R
R/W
RR
R
R/W
Initial Value
0
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