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參數(shù)資料
| 型號： | R5F2123AKFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 30/38頁 |
| 文件大小： | 473K |
| 代理商： | R5F2123AKFP |
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Section 2 CPU
Rev. 2.00 Aug. 28, 2007 Page 24 of 1106
REJ09B0230-0200
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly in memory.
Delayed Branching: Unconditional branch instructions means the delayed branch instructions.
With a delayed branch instruction, the branch is made after execution of the instruction
immediately following the delayed branch instruction. This minimizes disruption of the pipeline
when a branch is made. The conditional branch instructions have two types of instructions:
conditional branch instructions and delayed branch instructions.
Table 2.3
Delayed Branch Instructions
CPU in this LSI
Description
Example of Other CPUs
BRA
TRGET
ADD
R1,R0
ADD is executed before branch to TRGET.
ADD.W R1,R0
BRA
TRGET
Multiply/Multiply-and-Accumulate Operations: A 16
× 16 → 32 multiply operation is
executed in one to two cycles, and a 16
× 16 + 64 → 64 multiply-and-accumulate operation in two
to three cycles. A 32
× 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and-
accumulate operation are each executed in two to four cycles.
T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is
performed according to whether the result is True or False. Processing speed has been improved
by keeping the number of instructions that modify the T bit to a minimum.
Table 2.4
T Bit
CPU in this LSI
Description
Example of Other CPUs
CMP/GE
R1,R0
When R0
≥ R1, the T bit is set.
CMP.W R1,R0
BT
TRGET0
When R0
≥ R1, a branch is made to TRGET0. BGE
TRGET0
BF
TRGET1
When R0 < R1, a branch is made to TRGET1. BLT
TRGET1
ADD
#
1,R0
The T bit is not changed by ADD.
SUB.W #1,R0
CMP/EQ
#0,R0
When R0 = 0, the T bit is set.
BEQ
TRGET
BT
TRGET
A branch is made when R0 = 0.
Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword
immediate data is not placed in the instruction code. It is placed in a table in memory. The table in
memory is accessed with the MOV immediate data instruction using PC relative addressing mode
with displacement.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F2123AKFP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 96KB FLASH 3.3V/5V 48LQFP - Trays 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 96KB FLASH 48LQFP |
| R5F2123AKFP#V0 | 功能描述:IC R8C/23 MCU FLASH 48LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/23 標準包裝:96 系列:PIC® 16F 核心處理器:PIC 芯體尺寸:8-位 速度:20MHz 連通性:I²C，SPI 外圍設(shè)備:欠壓檢測/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):11 程序存儲器容量:3.5KB（2K x 14） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:128 x 8 電壓 - 電源 (Vcc/Vdd):2.3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 包裝:管件 |
| R5F2123CJFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:MCU |
| R5F2123CJFP#U0 | 功能描述:IC R8C/23 MCU FLASH 48LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/23 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標準包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設(shè)備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲器容量:384KB（384K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b，D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 產(chǎn)品目錄頁面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
| R5F2123CJFP#UO | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 128KB Flash 3.3V/5V 48-Pin LQFP Tray |
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