參數(shù)資料
型號: R5F21207KFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 19/45頁
文件大?。?/td> 418K
代理商: R5F21207KFP
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Rev.2.00 Aug 27, 2008
Page 26 of 41
REJ03B0120-0200
NOTES:
1.
Topr = -40
°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified.
2.
This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2
≥ 1.0 V.
3.
To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the
VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1.
4.
tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30s or more if -20
°C ≤ Topr ≤ 125°C, maintain tw(por1)
for 3,000s or more if -40
°C ≤ Topr < -20°C.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
Table 5.8
Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical Characteristics(3)
Symbol
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
Vpor1
Power-on reset valid voltage(4)
0.1
V
Vpor2
Power-on reset or voltage monitor 1 valid voltage
0
Vdet1
V
trth
External power VCC rise gradient
VCC
≤ 3.6 V
20(2)
mV/msec
VCC
> 3.6 V
20(2)
2,000
mV/msec
× 32
1
fOCO-S
Vdet1(3)
Vpor1
tw(por1)
Vdet1(3)
Vpor2
2.0 V
trth
External power Vcc
Internal reset signal
(“L” valid)
Sampling time(1, 2)
td(Vdet1-A)
× 32
1
fOCO-S
NOTES:
1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit of
Hardware Manual for details.
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