參數(shù)資料
型號(hào)： R5F21182DSP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO20
封裝： 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20
文件頁數(shù)： 20/41頁
文件大?。?/td> 725K
代理商： R5F21182DSP
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Rev.1.40
Apr 14, 2006
Page 27 of 38
REJ03B0124-0140
NOTES:
1.
This condition is not applicable when using with Vcc
≥ 1.0 V.
2.
When turning power on after the time to hold the external power below effective voltage (Vpor1) exceeds10 s, refer to Table
3.
tw(por2) is the time to hold the external power below effective voltage (Vpor2).
NOTES:
1.
When not using voltage monitor 1, use with Vcc
≥ 2.7 V.
2.
tw(por1) is the time to hold the external power below effective voltage (Vpor1).
Figure 5.3
Reset Circuit Electrical Characteristics
Table 5.8
Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset)
Symbol
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
Vpor2
Power-on reset valid voltage
-20
°C ≤ Topr ≤ 85°C
Vdet1
V
tw(Vpor2-Vdet1) Supply voltage rising time when power-on reset is
-20
°C ≤ Topr ≤ 85°C,
tw(por2)
≥ 0s(3)
100
ms
Table 5.9
Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset)
Symbol
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
Vpor1
Power-on reset valid voltage
-20
°C ≤ Topr ≤ 85°C
0.1
V
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
0
°C ≤ Topr ≤ 85°C,
tw(por1)
≥ 10 s(2)
100
ms
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
-20
°C ≤ Topr < 0°C,
tw(por1)
≥ 30 s(2)
100
ms
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
-20
°C ≤ Topr < 0°C,
tw(por1)
≥ 10 s(2)
1ms
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
0
°C ≤ Topr ≤ 85°C,
tw(por1)
≥ 1 s(2)
0.5
ms
NOTES:
1. Hold the voltage inside the MCU operation voltage range (Vccmin or above) within the sampling time.
2. The sampling clock can be selected. Refer to 7. Voltage Detection Circuit for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 7. Voltage Detection Circuit for details.
Vdet1(3)
Vpor1
Internal
reset signal
(“L” valid)
tw(por1)
tw(Vpor1–Vdet1)
Sampling time(1, 2)
Vdet1(3)
1
fRING-S
× 32
1
fRING-S
× 32
Vpor2
Vccmin
tw(por2) tw(Vpor2–Vdet1)
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