參數(shù)資料
型號： R5F21112FP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù)： 32/32頁
文件大小： 343K
代理商： R5F21112FP
R8C/11 Group
2. Central Processing Unit (CPU)
Rev.1.60
Jan 27, 2006
page 7 of 26
REJ03B0034-0160
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
Data registers(1)
Address registers(1)
Frame base registers(1)
Program counter
Interrupt table register
User stack pointer
Interrupt stack pointer
Static base register
Flag register
NOTES:
1.
A regist er bank comprises t hese regist ers. Two set s of regist er banks are provided
R0H (high-order of R0)
b15
b8 b7
b0
R3
INTBH
USP
ISP
SB
C
D
Z
S
B
O
I
U
IPL
R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
b31
R3
R2
A1
A0
FB
b19
INTBL
b15
b0
PC
b19
b0
b15
b0
FLG
b15
b0
b15
b0
b7
b8
Reserved bit
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
Figure 2.1 CPU Register
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