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參數(shù)資料
| 型號： | R5F21102DFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 2/30頁 |
| 文件大?。?/td> | 270K |
| 代理商： | R5F21102DFP |
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R8C/10 Group
2. Central Processing Unit (CPU)
Rev.1.60
Jan 27, 2006
page 8 of 25
REJ03B0035-0160
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative address-
ing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0
can be combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch
between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag
is set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
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| R5F21102FP | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 8KB Flash 3.3V/5V 32-Pin LQFP 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 8KB FLASH 3.3V/5V 32LQFP - Trays 制造商:Renesas Electronics Corporation 功能描述:16BIT MCU FLASH SMD 21102 LQFP32 |
| R5F21102FP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 8KB Flash 3.3V/5V 32-Pin LQFP Tray 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 8KB FLASH 3.3V/5V 32LQFP - Trays 制造商:Renesas Electronics Corporation 功能描述:IC R8C MCU FLASH 8K 32LQFP |
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