
R5101G
11
OPERATION
M When VDD is turned on and Input Voltage reaches Vstart (nearly equal 0.8V), the output of RESET pin
becomes “L” level.
N An External Capacitor starts to be charged through the CD pin when an Output Voltage of the Voltage
Regulator, VOUT, crosses the Released Voltage, +VDET, from Lower to Higher. The VRESET is kept “L” level
until Voltage of the CD pin, VCD, reaches to the Vref2H, about 1.0V, and after that the VRESET becomes to
“H” level.
tPR: Time interval between the timing of starting edge of forcing voltage to VDD pin and the timing of reverse
the voltage level of VRESET .
tPR can be set by connecting an external capacitor to CD pin, tPR can be calculated as shown below; tPR(ms)
≈
13000
× CD (F); CD means a value of an external capacitor connected to CD pin.
O When the voltage level of VCD reaches to the Vref2H, the external capacitor starts to be charged through the
CTW pin and the watchdog timer begins to operate.
P The operation mode for the external capacitor changes from charging mode to discharging mode through C
TW
pin when the voltage level of C TW pin, V CTW, reaches to the Vref2H.
Q While the C TW pin is on the discharging mode, if a clock pulse is entered (synchronous with a rising edge of
the pulse), the operation mode of C TW pin changes from discharging mode to charging mode. And the
external capacitor connected to C TW pin is charged until its voltage level reaches to Vref2H.
R While the C TW pin is on the discharging mode, if V CTW level drops to Vref2L, about 0.2V without clock pulse
to CLK pin, the voltage level of Reset pin becomes from “H” to “L”.
Watchdog Timeout period, tWD,: Discharging Time of C TW pin level from Vref2H to Vref2L
tWD can be set by connecting an external capacitor to C W pin, tWD can be calculated as shown below; tWD
(ms)
≈ 10000× C W (F); CW means a value of an external capacitor connected to CW pin.
S CTW pin is changed to charging mode from discharging mode when the Reset signal is generated.
Reset timeout period of the watchdog timer, tWR,: Time interval between Charging time of the CTW pin from
Vref2L to Vref2H. tWR can be calculated by the next equation as shown below; tWR (ms)
≈ tWD/10
T The Output Voltage level of RESET pin becomes from “H” to “L”, or a Reset signal is generated when an
output voltage of the Voltage Regulator drops to a level at equal or less than -VDET.
U The watchdog timer will be halted when a Voltage level of CE pin becomes to “L”. In this case, only the
watchdog timer is stopped and monitoring the output voltage is continued. After that, if the voltage level of
CE pin becomes to “H”, C TW pin starts to be on charging mode.