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參數(shù)資料
| 型號(hào)： | R485WPBB |
| 英文描述： | DIODE ZENER SINGLE 200mW 16.1Vz 10mA-Izt 0.02547 0.05uA-Ir 12 SOD-323 3K/REEL |
| 中文描述： | R485型光波接收機(jī)2.488磁錄密度/有時(shí)鐘恢復(fù)s應(yīng)用 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 134K |
| 代理商： | R485WPBB |
Advance Data Sheet, Rev. 1
October 2001
Recovery for 2.488 Gbits/s Applications
R485-Type Lightwave Receiver with Clock
Agere Systems Inc.
7
PWB Layout Guidelines
I
The data and clock outputs are designed to drive 50
loads.
I
Clock and data output traces must be controlled-impedance lines and the termination impedance must match
the line impedance. Avoid 90
°
bends in the traces. Paired lines (i.e., DATA and DATA) must be equal in length.
I
Data and clock output lines should be as short and straight as possible and should be shielded from noise
sources to prevent noise from feeding back into the receiver.
I
Use high-quality multilayer printed-wiring boards. A ground plane should occupy the area directly beneath the
receiver.
1-934(F)xxx
Note 1: Data and clock outputs must be ac-coupled on customer board. Use a 0.1
μ
F chip capacitor with a low ESR. For optimum receiver per-
formance, all four outputs must be terminated in equivalent loads, even if some of the outputs are not being used.
Note 2: The 0.1
μ
F V
CC
power supply bypass capacitors should be high-quality, low ESR chip capacitors that are located as close as possible to
the appropriate power supply leads and should provide a low inductance path to the ground plane.
Figure 4. Biasing and Interfacing to the R485-Type 2.5 Gbits/s Receiver
8, 22
5
6
10
11
CLOCK
CLOCK
DATA
DATA
50
TRANSMISSION
LINE (4X)
4, 7, 9, 12,
14—17, 19, 20
2.2
μ
F
15
μ
F
+5 V
0.1
μ
F
NOTE 1
50
+
V
CC
1
μ
H
0.1
μ
F
NOTE 2
LOS (FLAG)
3
0.1
μ
F
NIC
1
0.1
μ
F
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