參數(shù)資料
型號(hào): R480WPAA
英文描述: R480-Type Lightwave Receiver with CML Data Output for up to 2.488 Gbits/s Applications
中文描述: R480 -高達(dá)2.488磁錄密度型光波接收機(jī)CML數(shù)據(jù)輸出/ s應(yīng)用
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 76K
代理商: R480WPAA
6
Agere Systems Inc.
R480-Type Lightwave Receiver with CML Data Output
for up to 2.488 Gbits/s Applications
Data Sheet, Rev. 1
September 2001
PWB Layout Guidelines
I
The data outputs are designed to drive 50
loads.
I
Data output traces must be controlled-impedance lines and the termination impedance must match the line
impedance. Avoid 90
°
bends in the traces. Paired lines (i.e., DATA and DATA) must be equal in length.
I
Data output lines should be as short and straight as possible and should be shielded from noise sources to pre-
vent noise from feeding back into the receiver.
I
Use high-quality multilayer printed-wiring boards. A ground plane should occupy the area directly beneath the
receiver.
1-934(C)d
Note 1: Data outputs must be ac-coupled on customer board. Use a 0.1
μ
F chip capacitor with a low ESR. For optimum receiver performance,
both data outputs must be terminated in equivalent loads, even if one of the outputs is not being used.
Note 2: The 0.1
μ
F V
CC
power supply bypass capacitors should be high-quality, low ESR chip capacitors that are located as close as possible to
the appropriate power supply leads and should provide a low-inductance path to the ground plane.
Figure 1. Biasing and Interfacing to the R480-Type 2.5 Gbits/s Receiver
8, 22
10
11
23
DATA
DATA
OILV
50
TRANSMISSION
LINE (2X)
LOS (FLAG)
4, 7, 9, 12,
14—17, 19, 20
3
2.2
μ
F
15
μ
F
+5 V
0.1
μ
F
NOTE 1
50
+
V
CC
1
μ
H
0.1
μ
F
NOTE 2
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