參數(shù)資料
型號(hào)： R1151N3.1B-TR
英文描述： Analog IC
中文描述： 模擬IC
文件頁(yè)數(shù)： 6/26頁(yè)
文件大小： 426K
代理商： R1151N3.1B-TR
Rev. 1.11
- 6 -
I
TECHNICAL NOTES
When using these ICs, consider the following points:
In these ICs, phase compensation is made for securing stable operation even if the load current is varied. For this purpose, be
sure to use as much as 10
μ
F capacitor as C
L
with good frequency characteristics and ESR (Equivalent Series Resistance).
The best suitable equivalent series resistor value (ESR) is approximately 1
.
If the ESR of the output capacitor is too large, output may be unstable, therefore fully evaluation is necessary.
Make V
DD
and GND line sufficient. When their impedance of these is high, noise pickup or unstable operation may be the
result. Connect a capacitor with a capacitance value of as much as 10
μ
F between V
DD
and GND as close as possible to these
pins.
Set external components, especially output capacitor, as close as possible to the ICs.
Refer to the next equation to calculate the output delay time of C version and decide the capacitance value for the delay time.
tPLH =2.31
×
C/(300
×
10
-9
)
C: Capacitance value (F)
Recommended pull-up resistance (R1) value is 470k
. If the value is too small, released voltage may be shift, therefore, use
10k
or more value resistor.
I
TEST CIRCUITS
R1151NxxC
3
6
5
1
2
4
R1
C1
C2
PNP
VIN
VDET
IOUT
R1151NxxC
3
6
5
1
2
4
C1
C2
PNP
VIN
IOUT
Fig.1 Standard test Circuit
R1=470k
C1=220pF, C2=10
μ
F
Fig.2 Supply Current Test Circuit
C1=220pF, C2=10
μ
F
R1151NxxC
3
6
5
1
2
4
C1
C2
PNP
VIN
IOUT
P.G.
R1151NxxC
3
6
5
1
2
4
C1
C2
PNP
VIN
IOUT
P.G.
Fig.3 Ripple Rejection, Line Transient Response Test
Circuit C1=220pF, C2=10
μ
F
Fig.4 Load Transient Response Test Circuit
C1=220pF, C2=10
μ
F
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