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  • 參數(shù)資料
    型號(hào): R1130H281B-T2
    廠商: RICOH COMPANY LTD
    元件分類: 固定正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器
    英文描述: 2.8 V FIXED POSITIVE LDO REGULATOR, 0.34 V DROPOUT, PDSO6
    封裝: SOT-89, 5 PIN
    文件頁(yè)數(shù): 16/24頁(yè)
    文件大?。?/td> 739K
    代理商: R1130H281B-T2
    23
    4317K–AVR–03/2013
    AT90PWM2/3/2B/3B
    EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to
    0b00 unless the EEPROM is busy programming.
    Bit 3 – EERIE: EEPROM Ready Interrupt Enable
    Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
    EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
    rupt when EEWE is cleared. The interrupt will not be generated during EEPROM write or SPM.
    Bit 2 – EEMWE: EEPROM Master Write Enable
    The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
    When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
    the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
    been written to one by software, hardware clears the bit to zero after four clock cycles. See the
    description of the EEWE bit for an EEPROM write procedure.
    Bit 1 – EEWE: EEPROM Write Enable
    The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
    and data are correctly set up, the EEWE bit must be written to one to write the value into the
    EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-
    erwise no EEPROM write takes place. The following procedure should be followed when writing
    the EEPROM (the order of steps 3 and 4 is not essential):
    1.
    Wait until EEWE becomes zero.
    2.
    Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory
    Control and Status Register) becomes zero.
    3.
    Write new EEPROM address to EEAR (optional).
    4.
    Write new EEPROM data to EEDR (optional).
    5.
    Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
    6.
    Within four clock cycles after setting EEMWE, write a logical one to EEWE.
    The EEPROM can not be programmed during a CPU write to the Flash memory. The software
    must check that the Flash programming is completed before initiating a new EEPROM write.
    Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
    Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader
    programming.
    Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
    EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
    interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
    interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
    during all the steps to avoid these problems.
    Table 6-1.
    EEPROM Mode Bits
    EEPM1
    EEPM0
    Programming
    Time
    Operation
    0
    3.4 ms
    Erase and Write in one operation (Atomic Operation)
    0
    1
    1.8 ms
    Erase Only
    1
    0
    1.8 ms
    Write Only
    1
    Reserved for future use
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