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參數(shù)資料
| 型號： | QS5LV93180Q |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 3.3V的低偏移的CMOS PLL時鐘驅(qū)動器，帶有集成環(huán)路濾波器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 62K |
| 代理商： | QS5LV93180Q |
4
INDUSTRIAL TEMPERATURE RANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE
Symbol
t
SKR
t
SKF
t
PW
t
J
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Parameter
(1)
Min.
—
—
Max.
300
300
Unit
ps
ps
ns
ns
ps
ms
ns
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/2
(2)
Output Skew Between Falling Edges, Q
0
-Q
4
and Q/2
(2)
Pulse Width, Q
0
-Q
4
, Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter
(4)
SYNC Input to Feedback Delay
(5)
SYNC to Phase Lock
Output Enable Time, OE/
RST
LOW to HIGH
(3)
T
CY
/2
0.4
— 0.15
500
—
0
T
CY
/2 + 0.4
0.15
500
10
14
Output Disable Time, OE/
RST
HIGH to LOW
(3)
0
14
ns
Output Rise/Fall Times, 0.8V
~
2V
0.3
2
ns
NOTES:
1. See Test Loads and Waveforms for test load and termnation.
2. Skew specifications apply under identical environments (loading, temperature, V
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. t
PD
measured at device inputs at 0.5V
DD
, Q output at 80MHz.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5LV931-80Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5U12 | 制造商:ROHM 制造商全稱:Rohm 功能描述:2.5V Drive Nch+SBD MOS FET |
| QS5U12_1 | 制造商:ROHM 制造商全稱:Rohm 功能描述:2.5V Drive Nch+SBD MOS FET |
| QS5U12TR | 功能描述:MOSFET N-CH 30V 2A TSMT5 RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| QS5U13 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Small switching (30V, 2.0A) |
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