參數(shù)資料
型號: QS5LV93150Q
廠商: Integrated Device Technology, Inc.
英文描述: 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
中文描述: 3.3V的低偏移的CMOS PLL時鐘驅動器,帶有集成環(huán)路濾波器
文件頁數(shù): 5/8頁
文件大?。?/td> 62K
代理商: QS5LV93150Q
5
INDUSTRIAL TEMPERATURE RANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
30pF
300
6.0V
OUTPUT
V
DD
OUTPUT
1.0ns
1.0ns
2.0V
0.8V
3.0V
0V
V
th
= 0.5V
DD
t
R
t
F
0V
0.5V
DD
t
PW
CONTROL
INPUT
ENABLE
DISABLE
3V
0V
3.0V
0V
0.5V
DD
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
SWITCH
CLOSED
t
PZH
0.3V
0.3V
t
PZL
t
PLZ
t
PHZ
0.5V
DD
V
OH
V
OL
100
100
2.0V
0.8V
3.0V
0.5V
DD
AC TEST LOADS AND WAV EFORMS
Test Circuit 1
CMOS Input Test Waveform
CMOS Output Waveform
Test Circuit 2
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timng parameters.
Enable and Disable Times
相關PDF資料
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