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參數(shù)資料
| 型號(hào)： | QS5LV931-50Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | QS5LV931-50Q |
5
INDUSTRIAL TEMPERATURE RANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
30pF
300
6.0V
OUTPUT
V
DD
OUTPUT
1.0ns
1.0ns
2.0V
0.8V
3.0V
0V
V
th
= 0.5V
DD
t
R
t
F
0V
0.5V
DD
t
PW
CONTROL
INPUT
ENABLE
DISABLE
3V
0V
3.0V
0V
0.5V
DD
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
SWITCH
CLOSED
t
PZH
0.3V
0.3V
t
PZL
t
PLZ
t
PHZ
0.5V
DD
V
OH
V
OL
100
100
2.0V
0.8V
3.0V
0.5V
DD
AC TEST LOADS AND WAV EFORMS
Test Circuit 1
CMOS Input Test Waveform
CMOS Output Waveform
Test Circuit 2
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timng parameters.
Enable and Disable Times
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| QS5LV93166Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV931-66Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV93180Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV931-80Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5U12 | 制造商:ROHM 制造商全稱:Rohm 功能描述:2.5V Drive Nch+SBD MOS FET |
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