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參數(shù)資料
| 型號： | QS5LV919 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 3.3V的低偏移的CMOS PLL時鐘驅動器，帶有集成環(huán)路濾波器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 98K |
| 代理商： | QS5LV919 |
6
INDUSTRIAL TEMPERATURE RANGE
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ANALOG V
CC
ANALOG GND
DIGITAL
GND
DIGITAL
V
CC
BOARD GND
BOARD V
CC
0.1
μ
F
High
Freq.
Bypass
10
μ
F
Low
Freq.
Bypass
A separate Analog power supply is not necessary
and should not be used. Following these pre-
scribed guidelines is all that is necessary to use
the QS5LV919 in a normal digital environment.
0.1
μ
F
Bypass
Figure 1. Recommended Analog Isolation Scheme for the QS5LV919
NOTES:
1. Figure 1 shows an analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation:
a. All analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage
transients.
b. The 10μF low frequency bypass capacitor and the 0.1μF high frequency bypass capacitor forma wide bandwidth filter that will mnimze the QS5LV919's sensitivity to voltage
transients fromthe systemdigital V
CC
supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital V
CC
and ground noise, V
CC
step deviations should not occur at the QS5LV919's
digital V
CC
supply. The purpose of the bypass filtering scheme shown in figure 1 is to give the QS5LV919 additional protection fromthe power supply and ground plane
transients that can occur in a high frequency, high speed digital system
2. The bypass capacitors can be ceramc chip capacitors. There should be a 0.1μF bypass capacitor between each of the other (digital) four V
CC
pins and the board ground plane.
This will reduce output switching noise caused by the QS5LV919 outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass capacitors
should also be tied as close to the QS5LV919 package as possible.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| QS5LV919100J | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV919100Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV919-100Q | 制造商:Integrated Device Technology Inc 功能描述: 制造商:QSI 功能描述: |
| QS5LV919133J | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV919133Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
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