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參數(shù)資料
| 型號： | QS5930T |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 低偏移的CMOS PLL時鐘驅(qū)動器，帶有集成環(huán)路濾波器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 57K |
| 代理商： | QS5930T |
4
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input
frequencies.
5. t
PD
measured at device inputs at 1.5V, Q output at 28MHz.
S WIT CHING CHARACT ERIS T ICS OV ER OPERAT ING RANGE
Symbol
t
SKR
t
SKF
t
PW
t
J
t
PD
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Parameter
(1)
Mn.
—
—
Max.
250
350
Unit
ps
ps
ns
ns
ps
ns
Output Skew Between Rising Edges, Q
0
-Q
4
(and Q/2)
(2)
Output Skew Between Falling Edges, Q
0
-Q
4
(and Q/2)
(2)
Pulse Width, Q
0
-Q
4
, Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter, F
I
> 33MHz
( 4)
SYNC Input to Feedback Delay
( 5)
Output Enable Time, OE/
RST
LOW to HIGH
( 3)
T
CY
/2
0.5
—
100
0
T
CY
/2 + 0.5
250
+400
7
Output Disable Time, OE/
RST
HIGH to LOW
( 3)
0
6
ns
Output Rise/Fall Times, 0.8V to 2V
0.4
1.5
ns
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