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參數(shù)資料
| 型號(hào)： | QS5917T-70TQ |
| 廠商： | QUALITY SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | PLL BASED CLOCK DRIVER, PDSO28 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | QS5917T-70TQ |
INDUSTRIAL TEMPERATURE RANGE
6
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
30pF
7.0V
OUTPUT
300
20pF
V
DD
OUTPUT
160
68
TEST CIRCUIT 1
TEST CIRCUIT 2
TEST CIRCUIT 2 is used for output enable/disable parameters.
TEST CIRCUIT 1 is used for all other timing parameters.
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5917T provides
for replication of incomng SYNC clock signals. Any manipulation of that
signal, such as frequency multiplying or inversion is performed by digital
logic following the PLL (see the block diagram). The key advantage of the
SIMPLIFIED DIAGRAM OF QS5917T FEEDBACK
The phase difference between the output and the input frequencies feeds
the VCO which drives the outputs. Whichever output is fed back, it will
stabilize at the same frequency as the input. Hence, this is a true negative
feedback closed loop system In most applications, the output will optimally
have zero phase shift with respect to the input. In fact, the internal loop filter
on the QS5917T typically provides within 150ps of phase shift between
input and output.
PLL circuit is to provide an effective zero propagation delay between the
output and input signals. In fact, adding delay circuits in the feedback path,
‘propagation delay’ can even be negative! A simplified schematic of the
QS5917T PLL circuit is shown below.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
be advanced by the amount of delay in the feedback path. All other outputs
will retain their proper relationships to that output.
Q
Q/
2
Q
VCO
/2
/2
PHASE
DETECTOR
INPUT
2xQ
TEST LOAD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QS5919-55TQX | Eight Distributed-Output Clock Driver |
| QS5919-70TJ | Eight Distributed-Output Clock Driver |
| QS5919-70TJX | Eight Distributed-Output Clock Driver |
| QS5919-70TQ | Eight Distributed-Output Clock Driver |
| QS5919-70TQX | Eight Distributed-Output Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5917T-70TQ8 | 制造商:Integrated Device Technology Inc 功能描述:CLK DRVR PLL, FILTER - Tape and Reel |
| QS5917T-70TQG | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 28-Pin QSOP Tube 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28QSOP - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:CLK DRVR PLL, FILTER |
| QS5917T-70TQG8 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 28-Pin QSOP T/R 制造商:Integrated Device Technology Inc 功能描述:CLK DRVR PLL, FILTER - Tape and Reel |
| QS5917TJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|LDCC|28PIN|PLASTIC |
| QS5917TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|SSOP|28PIN|PLASTIC |
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