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參數(shù)資料
| 型號(hào)： | QS5917T-132TQ |
| 廠商： | QUALITY SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | GIGATRUE 550 CAT6 PATCH 2 FT, SNAGLESS, BEIGE |
| 中文描述： | PLL BASED CLOCK DRIVER, PDSO28 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 62K |
| 代理商： | QS5917T-132TQ |
INDUSTRIAL TEMPERATURE RANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
1
J ULY 2000
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-5227/2
FUNCTIONAL BLOCK DIAGRAM
R
D
Q
Q
0
R
D
Q
Q
1
R
D
Q
Q
2
R
D
Q
Q
3
R
D
Q
Q
4
R
D
Q
Q
5
R
D
Q
Q/2
Q
RST
0
1
1
0
/2
VCO
LOOP
FILTER
PHASE
DETECTOR
1
0
FREQ_SEL
REF_SEL
LOCK
FEEDBACK
SYNC
0
SYNC
1
PLL_EN
2xQ
QS5917T
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
DESCRIPTION
The QS5917T Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to one of two reference clock inputs. Eight
outputs are available: Q
0
-Q
4
, 2xQ, Q/2, Q
5
. Careful layout and design
insures < 500ps skew between the Q
0
-Q
4
, and Q/2 outputs. The QS5917T
includes an internal RC filter which provides excellent jitter characteris-
tics and elimnates the need for external components. In addition, TTL
level outputs reduce clock signal noise. Various combinations of feed-
back and a divide-by-2 in the VCO path allow applications to be custom-
ized for linear VCO operation over a wide range of input SYNC fre-
quencies. The VCO can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5917T is designed for use in
high-performance workstations, multi-board computers, networking hardware,
and mainframe systems. Several can be used in parallel or scattered
throughout a systemfor guaranteed low skew, system-wide clock distri-
bution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FEATURES:
5V operation
2xQ output, Q/2 output, Q output
Outputs tri-state while
RST
low
Internal loop filter RC network
Low noise TTL level outputs
< 500ps output skew, Q
0
-Q
4
PLL disable feature for low frequency testing
Balanced Drive Outputs ± 24mA
132MHz maximum frequency (2xQ output)
Functional equivalent to Motorola MC88915
ESD > 2000V
Latch-up > –300mA
Available in QSOP and PLCC packages
相關(guān)PDF資料 |
PDF描述 |
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| QS5917T | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5917T-70TJ | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5917T-70TQ | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5919-55TQX | Eight Distributed-Output Clock Driver |
| QS5919-70TJ | Eight Distributed-Output Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5917T-132TQ8 | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28QSOP - Tape and Reel |
| QS5917T-132TQG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CLK DRVR PLL, FILTER RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| QS5917T-132TQG8 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 28-Pin QSOP T/R 制造商:Integrated Device Technology Inc 功能描述:CLK DRVR PLL, FILTER. QSOP28 - Tape and Reel |
| QS5917T-132TQX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| QS5917T-70TJ | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 28-Pin PLCC Tube 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28PLCC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:CLK DRVR PLL, FILTER - Bulk |
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