參數資料
型號: QS53807ASO
英文描述: Ten Distributed-Output Clock Driver
中文描述: 十分布式輸出時鐘驅動器
文件頁數: 1/6頁
文件大小: 95K
代理商: QS53807ASO
1
QS532806/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2000
1999 Integrated Device Technology, Inc.
DSC-5783/-
c
QS532806/A
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
3.3V CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The QS532806 clock driver/buffer circuit can be used for clock buffering
schemes where low skew is a key parameter. The QS532806 offers two
banks of five inverting outputs. Designed in IDT's proprietary CMOS
process, these devices provide low propagation delay buffering with on-
chip skew of 0.7ns for same-transition, same-bank signals.
The QS532806 has on-chip series termnation resistors for lower noise
clock signals. The series resistor versions are recommended for driving
untermnated lines with capacitive loading and other noise sensitive clock
distribution circuits. These clock buffer products are designed for use in
high-performance workstations, embedded and personal computing sys-
tems. Several devices can be used in parallel or scattered throughout a
systemfor guaranteed low skew, system-wide clock distribution networks.
IN
A
IN
B
OE
A
OE
B
OB
5 -
OB
1
OA
5 -
OA
1
MON
5
5
FEATURES:
JEDEC compatible LVTTL level
10 low skew clock outputs
Monitor output
Clock inputs are 5V tolerant
Pinout and function compatible with QS5806
25
on-chip resistors for low noise
Input hysteresis for better noise margin
Guaranteed low skew:
0.7ns output skew (same bank)
0.9ns output skew (different bank)
1ns part-to-part skew
Std. and A speed grades
Available in QSOP and SOIC packages
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