參數(shù)資料
型號(hào)： QL901M-6PS680
廠商： Electronic Theatre Controls, Inc.
英文描述： SOCKET, PCB, RIGHT ANGLE, 26WAY; Connector type:Wire-to-Board; Gender:Socket; Ways, No. of:26; Pitch, lead:2.54mm; Termination method:Solder; Material, contact:Copper alloy; Plating, contact:0.3u Gold over 2u Nickel; Rows, No. of:2; RoHS Compliant: Yes
中文描述： QuickMIPS ESP家庭
文件頁(yè)數(shù)： 31/37頁(yè)
文件大?。?/td> 432K
代理商： QL901M-6PS680
QL901M QuickMIPS Data Sheet Rev B
31
U1_TXD_SIROUT_n
O
UART1 Transmitted Serial Data/SIR Transmitted Serial Data. This output transmits serial data from
either the UART or the IrDA block.
U2_RXD_SIRIN
I
UART2 Received Serial Data/SIR Received Serial Data. This input receives serial data for either the
UART or the IrDA block.
U2_TXD_SIROUT_n
O
UART2 Transmitted Serial Data/SIR Transmitted Serial Data. This output transmits serial data from
either the UART or the IrDA block.
Test Interface Signals
EJTAG_TCK
I
EJTAG Test Clock. This clock controls the updates to the TAP controller and the shifts through the
Instruction register or selected data registers. Both the rising and falling edges of EJTAG_TCK are
used.
EJTAG_TDI
I
EJTAG Test Data In. Serial test data is input on this pin and is shifted into the Instruction or data register.
This input is sampled on the rising edge of EJTAG_TCK.
EJTAG_TDO
O
EJTAG Test Data Out. The QuickMIPS chip outputs serial test data on this pin from the Instruction or
data register. This signal changes on the falling edge of EJTAG_TCK.
EJTAG_TMS
I
EJTAG Test Mode Select. This input is the control signal for the TAP controller. It is sampled on the
rising edge of EJTAG_TCK.
EJTAG_TRST
I
EJTAG Test Reset. This signal is asserted high asynchronously to reset the TAP controller, Instruction
register, and EJTAGBOOT indication.
EJTAG_DEBUGM
O
Debug Mode. This bit is asserted high when the MIPS 4Kc core is in Debug Mode. This output can be
used to bring the chip out of low power mode.
EJTAG_DINT
I
Debug Exception Request. Assertion high of this input indicates a debug exception request is pending.
The request is cleared when debug mode is entered. Requests that occur while the chip is in debug
mode are ignored.
Fabric Interface Signals
I/O<A>53:0
I/O
Programmable Input/Output/3-State/Bidirectional pin in Bank A.
I/O<B>71:0
I/O
Programmable Input/Output/3-State/Bidirectional pin in Bank B.
I/O<C>71:0
I/O
Programmable Input/Output/3-State/Bidirectional pin in Bank C.
I/O<D>53:0
I/O
Programmable Input/Output/3-State/Bidirectional pin in Bank D.
CLK<8:0>
I/O
Programmable Global Clock Pin. Tie to VCC or GND if unused.
INREF<A:D>
I/O
Differential I/O Reference Voltage. Connect to GND when using TTL, PCI or LVCMOS.
IOCTRL<A:D>
I/O
Low Skew I/O Control Pins. Tie to GND if unused.
TCLK
I
JTAG Clock. Tie to GND if unused.
TDI
I
JTAG Data In. Tie to VCC if unused.
TDO
O
JTAG Data Out. Leave unconnected if unused.
TMS
O
JTAG Test Mode Select. Tie to VCC if unused.
TRSTB
I
JTAG Reset. Tie to GND if unused.
Timer Interface Signals
TM_OVERFLOW
O
Timer Overflow. This output is asserted high when an internal timer overflows.
TM_ENABLE
I
Timer Enable. This signal is asserted high to enable the internal timer.
Miscellaneous Signals
BOOT<1:0>
I
Boot chip size. 00 = 8 bit, 01 = 16 bit, 10 = 32 bit, and 11 = reserved.
Table 27: Pin Descriptions (Continued)
Pin
I/O
Function
(Sheet 5 of 6)
相關(guān)PDF資料
PDF描述
QL901M-6PS680C Electrical Spring Connector; Contact Termination:Twist On; Wire Size (AWG):14-10; Body Material:Flame retardant nylon; Contact Material:Spring Steel; Pack Quantity:100; Series:512; Size:2-#18 up to 5-#12; Voltage Rating:600V RoHS Compliant: Yes
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