參數(shù)資料
型號(hào)： QL82SD-PT280
廠商： Electronic Theatre Controls, Inc.
英文描述： 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps
中文描述： 10高速總線LVDS串行鏈路的帶寬高達(dá)5Gbps的
文件頁(yè)數(shù)： 1/60頁(yè)
文件大?。?/td> 3838K
代理商： QL82SD-PT280
2002 QuickLogic Corporation
Preliminary
1
www.quicklogic.com
Device Highlights
LVDS SERDES Basic Features
10 High Speed Bus LVDS Serial Links—
bandwidth up to 5 Gbps
Eight Independent Bus LVDS serial
transceivers with operating speeds to 632
Mbps per channel
Two Independent Bus LVDS clock serial
transceivers with operating speeds to
400 MHz per channel
Integrated clock and data recovery (CDR)
with no external analog components
required
CDR bypass for applications with external
clock source
Programmable serial to parallel
configuration
10-bit data width—with
clock recovery
4-bit, 7-bit and 8-bit data widths—
with external clock
1-bit asynchronous level conversion
Fast Lock and Random (auto) Lock capable
Lock signal feedback
I/O support for LVTTL, LVCMOS, PCI,
GTL+, SSTL2, SSTL3, LVDS, LVPECL
Low Power/Independent power-down
mode for each SERDES channel
IEEE1149.1 JTAG Support &
boundary scan
Operation over PCB or backplane traces, or
across twisted pair cabling up to 25 m
Point-to-Point, Multi-Point, and Multi-Drop
Support
Pre-Emphasis Control on each LVDS
Channel Link
Extended Features
The following can be implemented into the
programmable logic:
UTOPIA Level 2, 16-bit wide System
interface (up to 50 MHz) with parity support
for ATM applications
UTOPIA Level 3 compatible 8-bit wide
system Interface (up to 100 MHz) with parity
support for ATM applications
CSIX-L1 32-bit switch fabric interface (up to
100 MHz)
Supports Generic 8,16,32-bit
microprocessor bus interface for
configuration, control and status monitoring
Supports Generic 32, 64-bit peripheral bus
interface for bridging functions
Flexible Programmable Logic
2,016 Programmable Logic Cells
536 K System Gates
Muxed architecture; non-volatile technology
Completely customizable for any digital
application
Dual Port SRAM Blocks
36 Dual Port SRAM Blocks
Configurable array sizes (by 2, 4, 9, 18)
< 3 ns access times, FIFO capable of over
300 MHz
Configurable as RAM or FIFO
QL82SD Device Data Sheet
相關(guān)PDF資料
PDF描述
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