參數(shù)資料
型號: QL8150-8PTN280M
廠商: QUICKLOGIC CORP
元件分類: FPGA
英文描述: FPGA, 640 CLBS, 188946 GATES, PBGA280
封裝: 0.80 MM PITCH, LEAD FREE, LFBGA-280
文件頁數(shù): 33/96頁
文件大?。?/td> 1607K
代理商: QL8150-8PTN280M
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
39
Figure 40: Eclipse II I/O Cell Output Enable Timing
Table 24: Eclipse II I/O Cell Output Timing
Symbol
Parameter
Value (ns)
Output Register Cell Only
Slow Slew Max
Fast Slew Max
t
OUTLH
Output Delay low to high (90% of H)
4.0
2.95
t
OUTHL
Output Delay high to low (10% of L)
3.5
2.49
t
PZH
Output Delay tri-state to high (90% of H)
4.96
2.93
t
PZL
Output Delay tri-state to low (10% of L)
4.87
2.84
t
PHZ
Output Delay high to tri-state
5.8
3.62
t
PLZ
Output Delay low to tri-state
5.58
3.4
tCOP
Clock-to-out delay (does not include clock tree delays)
5.49
3.3
Table 25: Output Slew Rates @ VCCIO = 3.3 V, T = 25
° C
Fast Slew
Slow Slew
Rising Edge
2.8 V/ns
1.0 V/ns
Falling Edge
2.86 V/ns
1.0 V/ns
Table 26: Output Slew Rates @ VCCIO = 2.5 V, T = 25
° C
Fast Slew
Slow Slew
Rising Edge
1.7 V/ns
0.6 V/ns
Falling Edge
1.9 V/ns
0.6 V/ns
Table 27: Output Slew Rates @ VCCIO = 1.8 V, T = 25
° C
Fast Slew
Slow Slew
Rising Edge
TBD
Falling Edge
TBD
L
H
L
H
tOUTLH
tOUTHL
L
H
Z
tPZH
L
H
Z
tPZL
L
H
Z
tPLZ
L
H
Z
tPHZ
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