參數(shù)資料
型號： QL8150-7PUN196C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 188946 GATES, PBGA196
封裝： 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, TFBGA-196
文件頁數(shù)： 31/96頁
文件大?。?/td> 1607K
代理商： QL8150-7PUN196C
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
37
Table 23: RAM Cell Synchronous and Asynchronous Read Timing
Symbol
Parameter
Value
Min
Max
RAM Cell Synchronous Read Timing
tSRA
RA setup time to RCLK: time the READ ADDRESS must be stable before the
active edge of the READ CLOCK
0.43 ns
-
t
HRA
RA hold time to RCLK: time the READ ADDRESS must be stable after the active
edge of the READ CLOCK
0 ns
-
tSRE
RE setup time to WCLK: time the READ ENABLE must be stable before the active
edge of the READ CLOCK
0.21 ns
-
tHRE
RE hold time to WCLK: time the READ ENABLE must be stable after the active
edge of the READ CLOCK
0 ns
-
t
RCRD
RCLK to RD: time between the active READ CLOCK edge and the time when the
data is available at RD
-
2.25 ns
RAM Cell Asynchronous Read Timing
rPDRD
RA to RD: time between when the READ ADDRESS is input and when the DATA
is output
-
1.99 ns
相關(guān)PDF資料
PDF描述
QL8150-7PUN196I FPGA, 640 CLBS, 188946 GATES, PBGA196
QL8150-7PUN196M FPGA, 640 CLBS, 188946 GATES, PBGA196
QL8150-8PT280C FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-8PT280I FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-8PT280M FPGA, 640 CLBS, 188946 GATES, PBGA280
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