參數(shù)資料
型號(hào)： QL8150-7PTN280M
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 188946 GATES, PBGA280
封裝： 0.80 MM PITCH, LEAD FREE, LFBGA-280
文件頁數(shù)： 2/96頁
文件大?。?/td> 1607K
代理商： QL8150-7PTN280M
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
10
become a greater issue with specific requirements for setup, hold, clock to out, and switching times. Eclipse II
has addressed these new system requirements and now includes a completely new I/O cell which consists of
programmable I/Os as well as a new cell structure consisting of three registers—Input, Output, and OE.
Eclipse II offers banks of programmable I/Os that address many of the bus standards that are popular today.
As shown in Figure 7 each bi-directional I/O pin is associated with an I/O cell which features an input register,
an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one
output multiplexers.
Figure 7: Eclipse II I/O Cell
The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown
in Figure 7, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input
buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers.
The select lines of the two-to-one multiplexers are static and must be connected to either VCC or GND.
For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the
logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the
array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to
be captured with fast, predictable set-up times without consuming internal logic cell resources. The comparator
and multiplexer in the input path allows for native support of I/O standards with reference points offset from
traditional ground.
For output functions, I/O pins can receive combinatorial or registered data from the logic array. For
combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For
registered output operation, the array logic drives the D input of the output cell register which in turn drives
the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be
E
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PAD
OUTPUT ENABLE
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REGISTER
INPUT
REGISTER
相關(guān)PDF資料
PDF描述
QL8150-7PUN196C FPGA, 640 CLBS, 188946 GATES, PBGA196
QL8150-7PUN196I FPGA, 640 CLBS, 188946 GATES, PBGA196
QL8150-7PUN196M FPGA, 640 CLBS, 188946 GATES, PBGA196
QL8150-8PT280C FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-8PT280I FPGA, 640 CLBS, 188946 GATES, PBGA280
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