參數(shù)資料
型號(hào)： QL8150-6PT280M
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 188946 GATES, PBGA280
封裝： 0.80 MM PITCH, LFBGA-280
文件頁(yè)數(shù)： 36/96頁(yè)
文件大?。?/td> 1607K
代理商： QL8150-6PT280M
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
41
Table 28: I/O Input Register Cell Timing
Symbol
Parameter
Value
Min
Max
tISU
Input register setup time: time the synchronous input of the flip-flop must be stable
before the active clock edge
2.15 ns
-
t
IHL
Input register hold time: time the synchronous input of the flip-flop must be stable after
the active clock edge
0 ns
-
tICO
Input register clock-to-out: time taken by the flip-flop to output after the active clock edge
-
0.3 ns
tIRST
Input register reset delay: time between when the flip-flop is “reset”(low) and when the
output is consequently “reset” (low)
-
0.82 ns
tIESU
Input register clock enable setup time: time “enable” must be stable before the active
clock edge
0.4 ns
-
t
IEH
Input register clock enable hold time: time “enable” must be stable after the active clock
edge
0 ns
-
Table 29: I/O Input Buffer Delays
Symbol
Parameter
Value
To get the total input delay add this delay to t
ISU
Min
Max
tSID (LVTTL)
LVTTL input delay: Low Voltage TTL for 3.3 V applications
-
0.82 ns
tSID (LVCMOS2)
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower
applications
-
0.82 ns
tSID (LVCMOS18) LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications
-
t
SID (GTL+)
GTL+ input delay: Gunning Transceiver Logic
-
0.94 ns
t
SID (SSTL3)
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V
-
0.94 ns
tSID (SSTL2)
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V
-
0.94 ns
t
SID (PCI)
PCI input delay: Peripheral Component Interconnect for 3.3 V
-
0.82 ns
相關(guān)PDF資料
PDF描述
QL8150-6PTN280C FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-6PTN280I FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-6PTN280M FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-6PUN196C FPGA, 640 CLBS, 188946 GATES, PBGA196
QL8150-6PUN196I FPGA, 640 CLBS, 188946 GATES, PBGA196
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