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| 型號(hào)： | QL7180-7PT280M |
| 英文描述： | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|280PIN |
| 中文描述： | 用戶可編程特殊功能的ASIC |的CMOS | BGA封裝| 280PIN |
| 文件頁(yè)數(shù)： | 1/26頁(yè) |
| 文件大?。?/td> | 315K |
| 代理商： | QL7180-7PT280M |
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QL7180 QuickDSP
TM
Data Sheet Rev B
1
QL7180 DSP Data Sheet
Combining Embedded DSP Blocks, Performance, Density
and Embedded RAM
1.0 Device Highlights
Clock Network
9 global clock networks
1 dedicated, 8 programmable
16 I/O (high drive) networks:
2 banks per I/O
20 Quad-net networks: 5 per quadrant
Programmable I/O
High performance enhanced I/O:
less than 3 ns Tco
Programmable slew rate control
Programmable I/O standards
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
8 independent I/O banks
3 register configuration: Input, Output, OE
Parameterized IP
Free parameterized IP administered with a
DSP Wizard
Supports multiple and hierarchical IP
instantiations
Applications
Signal processing operators
Signal processing functions
Networking / communications for VoIP
Speech / voice processing
Channel coding
High Speed Customizable Logic
0.25u, 5 layer metal CMOS process
2.5 V Vcc, 2.5 / 3.3 V drive capable I/O
512 programmable I/O
4,032 Logic Cells
660,000 max system gates
Muxed based architecture,
non-volatile technology
Completely customizable for any
digital applications
Dual Port SRAM
36 blocks of dual-port SRAM
2,304 bit dual port high performance
SRAM Blocks
Total of 82,900 bits
RAM / ROM / FIFO Wizard for automatic
configuration
Configurable and cascadable
Array sizes of 2, 4, 9, and 18
< 3 ns access times, 300+ MHz FIFO
Figure 1: Embedded QuickDSP Block Diagram
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