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5-1
Eclipse: Combining Performance, Density, and Embedded RAM
Updated 8/24/2000
Preliminary
Eclipse Family Data Sheet
Eclipse Family
Flexible Programmable Logic
.25u, 5 layer metal CMOS process
2.5 V Vcc, 2.5/3.3 V drive capable I/O
1.5 watts
Up to 4032 SuperCells
Up to 583,000 Max System Gates
Up to 512 I/O
Embedded Dual Port SRAM
Up to 36-2,304 bit Dual Port High
performance SRAM Blocks
Up to 82,900 RAM bits
RAM/ROM/FIFO Wizard for automatic
configuration
Configurable and Cascadable
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Phase Lock Loop (PDLL)
4 PLL/DLLs
Jitter<200 ps, Lock time <10 us
Capture and Lock range: 25 to 250 MHz
Programmable Multiply/Divide: 1x, 2x, 4x
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D
EVICE
H
IGHLIGHTS
Programmable I/O
High performance Enhanced I/O (EIO):
Less than 3 ns Tco
Programmable Slew Rate Control
Programmable I/O Standards
LVTTL, LVCMOS, PCI, GTL+, SSTL2,and SSTL3
8 Independent I/O Banks
3 Register Configuration: Input, Output, OE
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Advanced Clock Network
9 Global Clock Networks
1 dedicated
8 programmable
16 I/O (high drive) networks: 2 I/Os per bank
20 Quad-Net Networks: 5 per quadrant
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FIGURE 1. Embedded Eclipse Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
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| QL6600-7PS484C-5993 | 制造商:QuickLogic Corporation 功能描述: |
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