參數(shù)資料
型號： QL6250E-7PS484M
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 960 CLBS, 248160 GATES, PBGA484
封裝： 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484
文件頁數(shù)： 22/64頁
文件大?。?/td> 850K
代理商： QL6250E-7PS484M
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
29
Figure 32: RAM Cell Synchronous Write Timing
Table 17: RAM Cell Synchronous and Asynchronous Read Timing
Symbol
Parameter
Value
Min
Max
RAM Cell Synchronous Read Timing
t
SRA
RA setup time to RCLK: time the READ ADDRESS must be stable before the
active edge of the READ CLOCK
0.43 ns
-
tHRA
RA hold time to RCLK: time the READ ADDRESS must be stable after the active
edge of the READ CLOCK
0 ns
-
t
SRE
RE setup time to WCLK: time the READ ENABLE must be stable before the
active edge of the READ CLOCK
0.21 ns
-
t
HRE
RE hold time to WCLK: time the READ ENABLE must be stable after the active
edge of the READ CLOCK
0 ns
-
tRCRD
RCLK to RD: time between the active READ CLOCK edge and the time when the
data is available at RD
-
2.25 ns
RAM Cell Asynchronous Read Timing
r
PDRD
RA to RD: time between when the READ ADDRESS is input and when the DATA
is output
-
1.99 ns
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data
new data
WCLK
WA
WD
WE
RD
相關(guān)PDF資料
PDF描述
QL6250E-8PQ208C FPGA, 960 CLBS, 248160 GATES, PQFP208
QL6250E-8PQ208I FPGA, 960 CLBS, 248160 GATES, PQFP208
QL6250E-8PQ208M FPGA, 960 CLBS, 248160 GATES, PQFP208
QL6250E-8PS484C FPGA, 960 CLBS, 248160 GATES, PBGA484
QL6250E-8PS484I FPGA, 960 CLBS, 248160 GATES, PBGA484
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