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參數(shù)資料
| 型號： | QL6250E-7PS484I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 960 CLBS, 248160 GATES, PBGA484 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 64/64頁 |
| 文件大?。?/td> | 850K |
| 代理商： | QL6250E-7PS484I |
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2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
9
As designs become more complex and requirements more stringent, several application-specific I/O standards
have emerged for specific applications. I/O standards for processors, memories, and a variety of bus
applications have become commonplace and a requirement for many systems. In addition, I/O timing has
become a greater issue with specific requirements for setup, hold, clock to out, and switching times. Eclipse-
E has addressed these new system requirements and now includes a completely new I/O cell which consists
of programmable I/Os as well as a new cell structure consisting of three registers—Input, Output, and OE.
Eclipse-E offers banks of programmable I/Os that address many of the bus standards that are popular today.
As shown in Figure 7 each bi-directional I/O pin is associated with an I/O cell which features an input register,
an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one
output multiplexers.
Figure 7: Eclipse-E I/O Cell
The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown
in Figure 7, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input
buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers.
The select lines of the two-to-one multiplexers are static and must be connected to either VCC or GND.
For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the
logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the
array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to
be captured with fast set-up times without consuming internal logic cell resources. The comparator and
multiplexor in the input path allows for native support of I/O standards with reference points offset from
traditional ground.
For output functions, I/O pins can receive combinatorial or registered data from the logic array. For
combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For
registered output operation, the array logic drives the D input of the output cell register which in turn drives
E
R
Q
D
R
Q
D
E
R
Q
D
+
-
PAD
OUTPUT ENABLE
REGISTER
OUTPUT
REGISTER
INPUT
REGISTER
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| QL6250E-8PS484C | FPGA, 960 CLBS, 248160 GATES, PBGA484 |
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