- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄296940 > QL4058-2PQN208M (QUICKLOGIC CORP) FPGA, 1008 CLBS, 131328 GATES, PQFP208 PDF資料下載
參數(shù)資料
| 型號(hào)： | QL4058-2PQN208M |
| 廠商： | QUICKLOGIC CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MO-136, QFP-208 |
| 文件頁(yè)數(shù)： | 3/45頁(yè) |
| 文件大小： | 1332K |
| 代理商： | QL4058-2PQN208M |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)
2007 QuickLogic Corporation
QuickRAM Family Data Sheet Rev. M
11
JTAG
Figure 9: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the
least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response
to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan
Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of
a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with
the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests
for fuller verification of higher level system elements.
The 1149.1 standard requires the following three tests:
Extest Instruction. The Extest Instruction performs a Printed Circuit Board (PCB) interconnect test. This
test places a device into an external boundary test mode, selecting the boundary scan register to be
connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are
preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input
data for analysis.
Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this
test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the
functional data entering and leaving the device.
TCK
TMS
TRSTB
RDI
TDO
Instruction Decode
and
Control Logic
TAP Controller
State Machine
(16 States)
Instruction Register
Boundary-ScanRegister
(Data Register)
Mux
Bypass
Register
Mux
Internal
Register
I/O Registers
User Defined Data Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL4058-3PBN456C | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| QL4058-3PBN456I | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| QL4058-3PBN456M | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| QL4058-3PQN208C | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| QL4058-3PQN208I | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL4058-3PB456C | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-3PB456I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA|1008-CELL|CMOS|BGA|456PIN|PLASTIC |
| QL4058-3PB456M | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-3PQ208C | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL4058-3PQ208I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。