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參數(shù)資料
| 型號(hào)： | QL4016-4PF144M |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 320 CLBS, 61280 GATES, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件頁數(shù)： | 3/45頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | QL4016-4PF144M |
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2007 QuickLogic Corporation
QuickRAM Family Data Sheet Rev. M
11
JTAG
Figure 9: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the
least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response
to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan
Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of
a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with
the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests
for fuller verification of higher level system elements.
The 1149.1 standard requires the following three tests:
Extest Instruction. The Extest Instruction performs a Printed Circuit Board (PCB) interconnect test. This
test places a device into an external boundary test mode, selecting the boundary scan register to be
connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are
preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input
data for analysis.
Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this
test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the
functional data entering and leaving the device.
TCK
TMS
TRSTB
RDI
TDO
Instruction Decode
and
Control Logic
TAP Controller
State Machine
(16 States)
Instruction Register
Boundary-ScanRegister
(Data Register)
Mux
Bypass
Register
Mux
Internal
Register
I/O Registers
User Defined Data Register
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| QL4016-4PFN144M | FPGA, 320 CLBS, 61280 GATES, PQFP144 |
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